1. Field of the Invention
This invention relates to integrated circuits and more particularly to an improved method for reading a non-volatile memory array having over-erased memory cells within the array.
1. Description of the Relevant Art
There are many types of non-volatile memory, often called read only memory (ROM) or programmable read only memory (PROM). Non-volatile memory can be formed in either bipolar or MOS technology. Most MOS PROMs are based on one of three currently available technologies (i.e., EPROM, EEPROM or flash EPROM). Non-volatile MOS EPROMs are designed to perform in numerous similar ways, and can be achieved using many well-known technologies such as: (i) floating gate tunnel oxide, (ii) textured poly, (iii) metal nitride oxide silicon (MNOS), and (iv) EPROM-tunnel oxide (ETOX). Regardless of the form chosen, it is generally recognized that stacked polysilicon conductors are used to perform the program and erase functions. A comparison of the various non-volatile PROMs technologies is described in an article to S. Lai, et al., "Comparison and Trends in Today's Dominant E.sup.2 Technologies", Int'l Electron Devices Meeting Tech. Digest, (1986) pp. 580-583 (herein incorporated by reference).
A conventional MOS PROM memory array generally uses a single transistor for each cell within the array. The transistor is configured from a p-type substrate, having n-type source and drain regions provided within the substrate. In a flash EPROM device, the source is generally double-diffused. Thus, a double-diffused source region is defined to receive a n+type dopant in the same source region in which a previous n-type dopant was placed. Between the source and drain regions is a channel region, over which a tunnel oxide is formed. Placed upon the tunnel oxide is a floating polysilicon gate, and insulatively spaced over the floating polysilicon gate is a control polysilicon gate. Control polysilicon gates (control gates) are connected to respective word lines within the MOS PROM memory array. Drain regions are connected to respective bit lines within the MOS PROM array.
Using a flash EPROM cell as an example, an MOS PROM cell is typically programmed by applying a relatively high voltage to the control gate and a moderately high voltage to the drain. Hot electrons are thereby injected as a result of the electric field created between the control gate and drain. The hot electrons are injected upon the floating gate and trapped in the floating gate due to the fact that the floating gate is surrounded by dielectrics. Thus, a program operation functions to place a net negative charge upon the floating gate. Any read from a cell having programmed charge on the floating gate requires a higher read voltage on the control gate than cells which are not programmed. Higher voltage upon the programmed cell control gate is necessary to activate or ("turn-on") the single transistor MOS PROM cell. Further stated, a programmed MOS PROM cell requires a higher turn-on voltage at the control gate or (word line) than that of a unprogrammed cell.
Again using a flash EEPROM cell as a example, a programmed non-volatile MOS PROM cell is erased by extracting electron charge from the floating gate. Erasure is accomplished by electron tunneling and/or hot-hole injection. Typically, a high voltage is applied to the source of the cell while the gate is grounded. The drain is usually floating, and electron trapped upon the floating gate in a previous programming cycle are drawn (i.e., "tunneled") from the floating gate through the tunnel oxide and into the positively charged source.
The mechanism for programming and erasing a single transistor MOS PROM cell is described in reference to U.S. Pat. No. 4,958,321 (herein incorporated by reference). Described in Patent No. '321 is the program and erase description of a flash EPROM cell. It is understood, however, that program and erase of an EEPROM or UV-erased EPROM is performed or can be performed in substantially the same manner. That is, program is achieved by injection of electrons onto the floating gate, and erase is achieved by electron tunneling and/or hot-hole injection of those programmed electrons from the floating gate. Described in U.S. Pat. No. 5,077,691 are a number of drawbacks associated with flash EEPROM erase operations. Mentioned in Patent '691, is the problem of multiple power supply requirement and reverse voltage breakdown of the source during the erase operation. A double-diffused source region is typically employed to protect against the reverse voltage breakdown caused by the high positive voltage needed at the source during cell erase. Patent '691 teaches an advantage of using a highly negative voltage upon the control gate and a moderately positive voltage at the source during the erase operation. A moderately positive voltage at the source is employed to circumvent the necessity of a double diffused source needed if the source were heavily biased positive.
While Patent '691 teaches an improvement in the erase operation by utilizing a negative voltage upon the control gate, it does not suggest improvements in the read operation. That is, after a cell has been repeatedly erased under conditions of Fowler-Norheim tunneling, it may eventually acquire a somewhat positive potential. Thus, over numerous erase cycles, the floating gate will assume a condition often referred to as "bit over-erase". A description of bit over-erase is provided in reference to U.S. Pat. No. 5,335,198 (herein incorporated by reference).
Bit over-erase generally presents problems during the read operation. An understanding of over-erase problem begins by an understanding of the read operation. Namely, the read operation employs positive voltage exceeding the "turn on" threshold upon a control gate to be read, while all other control gates not to be read and associated with a mutually-connected bit line receive voltage less than a threshold amount. A cell to be read thereby utilizes a ground potential at the source region while the control gate is held at a positive potential, e.g, +5.0 volts. The drain region is generally held at a lower positive potential, e.g., between +1.0 to +4.0 volts. Under these conditions, an unprogrammed cell will conduct current of a greater amount than that of a programmed cell. Thus, the programmed state of the array can be read using this selective read operation. In an over-erased condition, an erased cell (a cell which is "non-programmed") will take on a net positive voltage upon the floating gate. The positive voltage presents itself as a negative threshold voltage. Accordingly, an over-erased cell functions essentially as a depletion-mode transistor.
It is important that only the cell of interest be read, and that all other mutually connected cells not be read. Accordingly, only the programmed/unprogrammed state of the cell of interest need be read in a read cycle. The non-selected cells, or cells not of interest, are provided 0.0 volts upon the control gate in an attempt to ensure their inoperability. Unfortunately, if the non-selected cells are depletion-mode transistors (i.e., have negative threshold voltage brought about by an over-erase condition), then the over-erased cells will,inadvertently be active causing leakage within the respective column bit line. Accordingly, an over-erased memory cell will disable an entire column of memory array. As used herein, the term "endurance" refers to the number of times a memory cell can be reprogrammed and erased with operability retained. If an over-erased condition causes inadvertent turn-on of a cell and inaccurate reading upon a column bit line, endurance of the corresponding memory cell is reduced. It is therefore important to maximize memory cell endurance by ensuring against inadvertent turn-on of over-erased cells without having to add complicated bit correction structures to the memory array. Conventional non-volatile memories employ bit correction circuitry which function to sense an over-erased cell and, as a result thereof, program back to a normal condition the over-erased memory cell. Sense and reprogram operations unduly adds complexity to the memory array and thereby reduces memory storage density.